Hardware Implementation of PAPR Reduction with Clipping and Filtering Technique for Mobile Applications

Abstract-Orthogonal frequency division multiplexing (OFDM) is preferred for mobile communications applications due to its increased data transmission capability. At one hand, it has advantages of being robust to multipath fading and possessing high data rate transmission capability, on the other hand it suffers from high peak to average power ratio (PAPR). In this paper FPGA implementation of clipping and filtering method have been implemented on Xilinx Spartan 3 Protoboard XC 3S 400 board for 4 QAM OFDM signals. The results obtained have been compared with National Instrument’s (NI) AWR visual system simulator and Matlab software simulations. FPGA implementation of pre-filtering and post clipping technique results with 2.2 dB PAPR, whereas, PAPR values obtained in the case of pre-clipping and post filtering method, are 10.6, 10.7 and 10.9 dB with NI’s AWR simulation, Matlab simulation and FPGA implementation respectively. When compared with original OFDM signal having 12.5 dB PAPR, FPGA implementation of pre-filtering and post-clipping reduces PAPR by 10.3 dB, whereas for the case of pre-clipping and post-filtering technique the reductions in PAPR are 1.6, 1.8 and 1.9 dB with FPGA implementation, Matlab and NI’s AWR software simulations respectively. Keyword-FPGA, OFDM, PAPR, BER, Clipping and filtering